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MICRF002BN Datasheet(PDF) 11 Page - Micrel Semiconductor |
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MICRF002BN Datasheet(HTML) 11 Page - Micrel Semiconductor |
11 / 13 page QwikRadio tm 11 July 1999 MICRF002 MICRF002 Micrel I/O Pin Interface Circuitry Interface circuitry for the various I/O pins of the MICRF002 is shown in Figures 1 through 6. Specific information regarding each of these circuits is discussed in the following sub-paragraphs. Not shown are ESD protection diodes which are applied to all input and output pins. 1. ANT Pin The ANT pin is internally AC-coupled via a 3pF capacitor, to an RF N-channel MOSFET, as shown in Figure 1. Impedance on this pin to VSS is quite high at low frequencies, and decreases as frequency increases. In the UHF frequency range, the device input can be modeled as 6.3k Ω in parallel with 2pF (pin capacitance) shunt to VSSRF. 2. CTH Pin Figure 2 illustrates the CTH pin interface circuit. CTH pin is driven from a P-channel MOSFET source-follower biased with approximately 10µA of bias current. Transmission gates TG1 and TG2 isolate the 6.9pF capacitor. Internal control signals PHI1/PHI2 are related in a manner such that the impedance across the transmission gates looks like a “resistance” of approximately 100k Ω. The DC potential on the CTH pin is approximately 1.6V 3. CAGC Pin Figure 3 illustrates the CAGC pin interface circuit. The AGC control voltage is developed as an integrated current into a capacitor CAGC. The attack current is nominally 15 µA, while the decay current is a 1/10th scaling of this, nominally 1.5 µA, so the attack/decay timeconstant ratio is fixed at 10:1. Signal gain of the RF/IF strip inside the IC diminishes as the voltage on CAGC decreases. Further discussion on setting the attack time constant is found in “Application Note TBD. Modification of the attack/decay ratio is possible by adding resistance from CAGC pin either to VDDBB or VSSBB, as desired. Both the Push and Pull current sources are disabled during SHUT, which holds the voltage across CAGC, and improves recovery time in duty-cycled applications. To further improve duty cycle recovery, both Push and Pull currents are increased by 45X for approximately 10msec after release of SHUT. This allows rapid recovery of any voltage droop on CAGC while in SHUT. 4. DO and WAKEB Output Pins The output stage for the signals DO and WAKEB is shown in Figure 4. The output is a 10µA push-10µA pull, switched current stage. Such an output stage is capable of driving CMOS-type loads. An external buffer-driver is recommended for driving high capacitance loads. 5. REFOSC Pin The REFOSC input circuit is shown in Figure 5. Input impedance is quite high (200k Ω). This is a Colpitts oscillator, with internal 30pF capacitors. This input is intended to work with standard ceramic resonators, connected from this pin to VSSBB, although a crystal may be used instead, where greater frequency accuracy is required. The resonators should not contain integral capacitors, since these capacitors are contained inside the IC. Externally applied signals should be AC-coupled, amplitude limited to approximately 0.5Vpp. The nominal DC bias voltage on this pin is 1.4V. 6. Control Inputs (SEL0, SEL1, SWEN, SHUT) Control input circuitry is shown in Figures 6a and 6b. The standard input is a logic inverter constructed with minimum geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large channel length device which functions essentially as a “weak” pullup to VDDBB. Typical pullup current is 5 µA, leading to an impedance to the VDDBB supply of typically 1M Ω. Figure 1 ANT Pin |
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