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HI-8477 Datasheet(PDF) 6 Page - Holt Integrated Circuits |
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HI-8477 Datasheet(HTML) 6 Page - Holt Integrated Circuits |
6 / 15 page FUNCTIONAL DESCRIPTION HOLT INTEGRATED CIRCUITS 6 OVERVIEW The HI-8477 and HI-8478 are autonomous ARINC 429 re- ceivers intended for applications where a host MCU is either undesirable or not otherwise needed. The parts contain an on-chip ARINC 429 line receiver and protocol logic to decode and capture selected ARINC 429 data words. The ARINC 429 word is made available to the application on 32 CMOS output pins, which may be used to directly control sub- system functions. The HI-8478 device provides data which is the complement of HI-8477. An on-chip ARINC 429 analog receiver operates from the same supply as the digital logic. Two input pins, RXA-R and RXB-R, require an external series resistor of 13 kOhm between the pin and ARINC 429 bus for proper signal level detection. With these resistors the inputs are lightning protected to RTCA/DO-160G, Section 22 Level 3 Pin Injection, Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B). Application Note AN-301 provides guidelines for enhanced lightning protection circuitry. Applications may wire the device outputs directly to logic, relay drivers, DACs, etc. It is therefore important to define the state of the outputs during the interval between system reset and the reception of a first, valid ARINC 429 word. The HI-8477 holds all BIT1:32 outputs in tri-state following reset. The pins have internal weak (60kOhm) pull-down re- sistors. This provision allows hardwiring 10kOhm resistors at each output to VDD or GND to set the initial state of the 32 bits. The HI-8478 does not have this feature; all BIT1:32 outputs will be logic “High” following reset. ARINC 429 LINE RECEIVER RESET OPERATION ARINC 429 WORD DECODER If even parity was received (error), the word is discarded. A 1MHz clock at CLKIN samples the outputs of the ARINC 429 receiver at ten times the nominal bit rate. The SPEED pin should be set to a zero when connecting the HI-8477 to a low-speed (12.5kb/s) ARINC 429 bus, or to a one for connec- tion to a high-speed (100kb/s) bus. The PARITY pin selects whether parity checking of incoming ARINC 429 words is enabled. If the PARITY pin is set high, the receiver logic checks for odd parity. If odd parity was received, the word is stored unaltered in the input shift register (see Figure 2). Setting the PARITY pin low disables parity checking and all ARINC 429 received words are passed to the input shift reg- ister unaltered. LABEL FILTERING PARALLEL OUTPUT DATA All properly encoded ARINC 429 received data words are captured by the input shift register. However, only words meeting user-specified label and SD values are then passed to the output latch (see Figure 2). Eight label match inputs, LLA:(7:0), and eight filter inputs, FILT(7:0) define the label match criteria. Setting a filter bit high enables matching for that bit of the received ARINC 429 label byte. If FILTn is high, the ARINC label bit must match the value at LLAn for the word to be accepted. Setting FILTn low, disables matching for that bit, declaring it a “don’t care” bit. Setting FILT(7:0) to 0x00 turns off label matching for all label bits; in this case the HI-8477 accepts all ARINC 429 labels. Judicious selection of LLA(7:0) and FILT(7:0) val- ues allows either a single ARINC 429 label to be accepted by the filter or a group of labels. For example, setting FILT(7:0) to 0xFC and LLA(7:0) to 0x80, accepts ARINC 429 labels 0x80 through 0x83 only (10 - 13 octal). Note that ARINC 429 defines the label bits as “big-endian”. Therefore received ARINC 429 bit 1 is the MSB (label bit 7), and ARINC received bit 8 is the LSB (label bit 0). Thus LLA7 and FILT7 compare ARINC bit 1, LLA6 and FILT6 compare ARINC bit 2, etc. ARINC bits 9 and 10 are the SD bits. Incoming ARINC 429 words captured in the input shift register may also be com- pared for SD matching as a condition for passing to the output latch. Taking the SDE pin high enables this feature. When SDE is high, ARINC bits 9 and 10 are compared with the state of the SD9 and SD10 input pins. Label filtering AND SDE matching criteria must be met to allow a re- ceived word to be passed to the output latch. Data is passed to the output latch one CLKIN period before the rising edge of the UPDATE pin and remains stable until a new valid and label-matching ARINC 429 word is re- ceived. UPDATE goes low as soon as the first bit of a po- tential new ARINC 429 word is detected by the receiver. HI-8477, HI-8478 |
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