TLE7184F

General Product Characteristics

Data Sheet

11

Rev. 1.1, 2011-04-08

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

4.4

Default State of Inputs

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

4.3.1

1) Not subject to production test, specified by design.

R

thJC

–

–5K/W

–

4.3.2

Junction to Ambient1)

R

thJA

–29

–

K/W

2)

2) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

Table 1

Default State of Inputs

Characteristic

State

Remark

Default state of ILx (if ILx left open -pull down)

Low

Low side MOSFETs off

Default state of IHx (if IHx left open - pull up)

High

High side MOSFETs off

Default state of RGS (if RGS left open - pull down)

Low

Error signal is reset and

the TLE7184F goes to

sleep

Default state of INH (if INH left open - pull down)

Low

no wake up by INH

Default state of SCDL (if SCDL left open - pull up)

High

Error signal is set; all

MOSFETs switched off

1) external capacitance < 25pF

High

no wake up by IFMA

Default state of IOV (if IOV left open - pull down)

Low

no Over Voltage detection

by IOV

Default state of DT (if DT left open)

max. dead time

max. dead time