5

FN4138.8

June 1, 2006

-

1.0

10

μA

-

5.0

-

pF

DIGITAL OUTPUTS

2.4

-

-

V

-

-

0.4

V

Output Three-State Leakage Current,

-10

1

10

μA

-10-

pF

TIMING CHARACTERISTICS

200

-

-

ns

50

-

-

ns

50

-

-

ns

DRDY Minimum High Pulse Width

(Notes 2, 7)

500

-

-

ns

Data Setup to SCLK Rising Edge

50

-

-

ns

Data Hold from SCLK Rising Edge

0-

-

ns

Data Read Access from Instruction Byte

(Note 7)

-

-

40

ns

Read Bit Valid from SCLK Falling Edge,

(Note 7)

-

-

40

ns

Last Data Transfer to Data Ready

(Note 7)

-

35

-

ns

RESET Low Pulse Width

(Note 2)

100

-

-

ns

SYNC Low Pulse Width

(Note 2)

100

-

-

ns

Oscillator Clock Frequency

(Note 2)

0.1

-

10

MHz

Output Rise/Fall Time

(Note 2)

-

-

30

ns

Input Rise/Fall Time

(Note 2)

-

-

1

μs

POWER SUPPLY CHARACTERISTICS

--

1.5

mA

--

2.0

mA

SCLK = 4MHz

-

-

3.0

mA

SB = ‘0’

-

15

32.5

mW

SB = ‘1’

-

5

-

mW

PSRR

(Note 3)

-

70

-

dB

NOTES:

2. Parameter guaranteed by design or characterization, not production tested.

3. Applies to both bipolar and unipolar input ranges.

4. These errors can be removed by re-calibrating at the desired operating temperature.

5. Applies after system calibration.

6. Fully differential input signal source is used.

7. See Load Test Circuit, Figure 10, R1 = 10k

8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.

10. These errors are on the order of the output noise shown in Table 1.

Electrical Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HI7191