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ZL2105EVK2 Datasheet(PDF) 8 Page - Intersil Corporation |
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ZL2105EVK2 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 36 page ZL2105 8 FN6851.2 March 30, 2011 3. Typical Application Circuit The following application circuit represents a typical implementation of the ZL2105. UVLO ILIM SCL SDA SALRT XTEMP DGND SA SYNC ZL2105 VDDP SW SW PGND PGND CP2 VR VDDP BST 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 VOUT 3.3V VIN 12V I 2C/SMBus ENABLE PGOOD CB 47nF CR 4.7µF CRA 4.7µF C25 10µF CDD 2.2µF CDR 100nF COUT 150µF LOUT 4.7µH CIN 100µF RVR 91 Ω F.B.* * Ferrite bead is optional for input noise suppression Figure 3. 12 V to 3.3 V / 3 A Application Circuit (10.8 V UVLO, 10 ms SS delay, 50 ms SS ramp, 12 V used for low-side FET driver) |
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Similar Description - ZL2105EVK2 |
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