MX29LV160AT datasheet(12/66 Pages) MCNIX

Part #	MX29LV160AT

Description	16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE and OE pins to VIL. CE is the power control

and selects the device. OE is the output control and

gates array data to the output pins. WE should remain at

VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address

on the device address inputs produce valid data on the

device data outputs.The device remains enabled for read

access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of

memory, the system must drive WE and CE to VIL, and

OE to VIH.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 1 and Table 2 indicate the

address space that each sector occupies. A "sector ad-

dress" consists of the address bits required to uniquely

select a sector. The Writing specific address and data

commands or sequences into the command register ini-

tiates device operations. Table 5 defines the valid regis-

ter command sequences. Writing incorrect address and

data values or writing them in the improper sequence

resets the device to reading array data. Section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

After the system writes the "read silicon-ID" and "sector

protect verify" command sequence, the device enters

the "read silicon-ID" and "sector protect verify" mode.

The system can then read "read silicon-ID" and "sector

protect verify" codes from the internal register (which is

separate from the memory array) on Q7-Q0. Standard

read cycle timings apply in this mode. Refer to the "read

silicon-ID" and "sector protect verify" Mode and "read

silicon-ID" and "sector protect verify" Command Se-

quence section for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE and RESET, the device

enter CMOS Standby with both pins held at Vcc ± 0.3V.

If CE and RESET are held at VIH, but not within the

range of VCC ± 0.3V, the device will still be in the standby

mode, but the standby current will be larger. During Auto

Algorithm operation, Vcc active current (ICC2) is required

even CE = "H" until the operation is completed. The de-

vice can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the devices are disabled. This will cause the output pins

to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of reset-

ting the device to reading array data. When the RESET

pin is driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write com-

mands for the duration of the RESET pulse. The device

also resets the internal state machine to reading array

data. The operation that was interrupted should be re-

initiated once the device is ready to accept another com-

mand sequence, to ensure data integrity.

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

The RESET pin may be tied to system reset circuitry. A

system reset would that also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET is asserted during a program or erase opera-

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