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MX9691L Datasheet(PDF) 9 Page - Macronix International |
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MX9691L Datasheet(HTML) 9 Page - Macronix International |
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9 / 41 page  9 MX9691L P/N:PM0546 REV. 1.1, JUL. 02, 1999 Symbol No. Type Description FCE[7:0]# 43-44, O Flash memory chip enable 7-0 : 46-47 (CMOS) In linear mode, These signals are decoded from port 601Dh 49-52 bit 7-5 when flash memory read or port 601Fh bit 7-5 when flash memory write. Decoding combination : bit7 bit6 bit5 FCE[7:0]# 0 0 0 11111110 0 0 1 11111011 0 1 0 11101111 0 1 1 10111111 1 0 0 11111101 1 0 1 11110111 1 1 0 11011111 1 1 1 01111111 In series mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set. PWD0#/WP# 32 O In linear mode, this signal is used as deep power-down (CMOS) control of flash memory chips of bank0. PWD0# is active low and also locks out erase or program operation providing data protection during power transitions. Power down pin PWD0# will be active if FA23=1. In series mode, this signal is used to protect the device from inadvertent programming or erasing. WP# is active low. PWD1#/SE# 64 O In linear mode, this signal is used as deep power-down (CMOS) control of flash memory chips of bank1. PWD1# is active low and also locks out erase or program operation providing data protection during power transitions. Power down pin PWD0# will be active if FA23=0. In series mode,this signal is used to spare area control. SE# is active low. FRY/FBY# 13 I Flash memory Ready/busy input: (CMOS) This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor. |
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