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6 MX9691A P/N:PM0539 REV. 1.0, OCT. 02, 1998 Symbol No. Type Description HOLD# 16 I/O In normal mode, this signal is input that is used as holding DSP clock down and release bus. Bus hold will be internally asserted also when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. This pin includes an pull-up resistor. HLDA# 73 I/O In normal mode, this signal is output that is used as ack to HOLD# signal. This signal will be internally sent to PCMCIA/ATA interface also when upgrade mode enable. In ICE debugging mode, this signal is input and ack to HOLD# when upgrade mode enable. This pin in cludes an pull-up resistor. XF#/CPURST# 74 O External flag, this pin can be directly written by one DSP instruction. Default inactive (logic high). In ICE debugging mode, this signal is used to reset CPU. Flash Memory Interface : Symbol No. Type Description FA19/CLE 12 O In random mode, this signal is used as flash memory chip high address line 19. In sequential mode, this signal is used as flash memory chip command latch enable. FA18/ALE/ 20 I/O In random mode, this signal is used as flash memory chip high address line 18. In sequential mode, this signal is used as flash memory chip address latch enable. This signal is used to select whether the MX9691A initializes in normal mode or in ICE debugging mode at power- on reset. If this pin go high, then the MX9691A will switch to normal mode at power-on reset,and if this pin remains low, then the MX9691 A will initializes in ICE debugging mode. This pin includes an internal pull-up resistor. ICEMODE ICE debugging mode select : ICEMODE=1 —> Normal mode ICEMODE=0 —> ICE debugging mode |
