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ISL80510EVAL1Z Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL80510EVAL1Z Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 14 page ISL80505 3 FN8770.0 September 8, 2015 Submit Document Feedback Pin Configuration ISL80505 (8 LD 3x3 DFN) TOP VIEW 2 3 4 1 5 8 7 6 VOUT VOUT FB GND VIN VIN ENABLE SS EPAD Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2 VOUT Regulated output voltage. A minimum 4.7µF X5R/X7R output capacitor is required for stability. See “External Capacitor Requirements” on page 10 for more details. 3 FB This pin is the input to the control loop error amplifier and is used to set the output voltage of the LDO. 4GND Ground 5ENABLE VIN independent chip enable. TTL and CMOS compatible. 6 SS External capacitor on this pin adjusts start-up ramp and controls inrush current. 7, 8 VIN Input supply; A minimum of 4.7µF X5R/X7R input capacitor is required for proper operation. See “External Capacitor Requirements” on page 10 for more details. - EPAD EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. |
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