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U74HCT7046G-S16-T Datasheet(PDF) 8 Page - Unisonic Technologies |
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U74HCT7046G-S16-T Datasheet(HTML) 8 Page - Unisonic Technologies |
8 / 16 page U74HCT7046 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 8 of 16 www.unisonic.com.tw QW-R502-851.A PHASE COMPARATORS. If the signal swing is between the standard HC family input logic levels, the signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14. Capacitive coupling is required for signals with smaller swings. Phase comparator 1 (PC1) This is an EXCLUSIVE-OR network. To obtain the maximum locking range, the signal and comparator input frequencies (fI) must have a 50% duty factor. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: ) ( V V COMPIN SIGIN DEMOUT CC φ φ π − = Where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The phase comparator gain is: ) r V / ( V K CC P π = As shown in Fig.1, the average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT) is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN). The average of VDEMOUT is equal to VCC/2 when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fO). As shown in Fig.2 it is the typical waveforms for the PC1 loop locked at fO. π Fig.1 Phase comparator 1: average output voltage versus input phase difference. SIGIN COMPIN VCOOUT PC1OUT VCOIN VCC GND Fig.2 Typical waveforms for PLL using phase comparator 1, loop locked at fO. The frequency capture range (2fc) is he frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the low-pass filter characteristics determine the capture range which can be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behavior of this type of phase |
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