2

P/N:PM0241

REV. 2.3, JUN. 20, 2003

MX23C1611

48 TSOP (Normal Type)

BYTE

A16

A15

A14

A13

A12

A11

A10

A9

A8

A19

VSS

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VSS

VSS

D15/A-1

D7

D14

D6

D13

D5

D12

D4

VCC

VCC

NC

D11

D3

D10

D2

D9

D1

D8

D0

OE

VSS

VSS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

MX23C1611

(Normal Type)

BLOCK DIAGRAM

Address

Buffer

Memory

Array

Page

Buffer

Page

Decoder

Word/

Byte

Output

Buffer

D0

D15/(D7)

A3

A19

A0/(A-1)

A2

CE

BYTE

OE

Note: Chip Enable active low input activates the chip's control logic, Address buffer and Page buffer.