9

FN6219.2

July 27, 2006

For sourcing:

For sinking:

Where:

• N = number of amplifiers (max = 4)

overheat.

Caution: For supply voltages greater then 20V, the

maximum power dissipation at 85°C ambient temperature

could be exceeded. For higher supply voltages the

maximum ambient temperature must be de-rated according

to the Package Power Dissipation curve Figure 27. The

maximum power dissipation is highly dependent upon the

thermal conductivity of the PCB. For lower thermal

conductivity boards use Figure 26.

Power Supply Bypassing Printed Circuit Board

Layout

As with any high frequency device, a good printed circuit

board layout is necessary for optimum performance. Lead

lengths should be as short as possible. The power supply

pin must be well bypassed to reduce the risk of oscillation.

connected to the ground plane, a single 4.7µF tantalum

to GND will suffice. This same capacitor combination should

be placed at each supply pin to ground if split supplies are to

supply rail.

Printed Circuit Board Layout

For good AC performance, parasitic capacitance should be

kept to minimum. Use of wire wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier's inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

Application Circuits

Sallen Key Low Pass Filter

A common and easy to implement filter taking advantage of

the wide bandwidth, low offset and low power demands of

the ISL55004. A derivation of the transfer function is

provided for convenience (See Figure 28).

Sallen Key High Pass Filter

Again this useful filter benefits from the characteristics of the

ISL55004. The transfer function is very similar to the low

pass so only the results are presented (See Figure 29).

PD

MAX

V

S

I

SMAX

V

S

V

OUTi

–

()

i1

=

n

∑

V

OUTi

R

Li

-----------------

×

+

×

=

PD

MAX

V

S

I

SMAX

V

OUTi

V

S

–

()

i1

=

n

∑

I

LOADi

×

+

×

=

ISL55004