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ISL6740IVZ Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6740IVZ Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 28 page  ISL6740, ISL6741 10 FN9111.6 December 2, 2011 Pin Descriptions VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency, fSW, and the output loading capacitance charge, Q, per output, the average output current can be calculated from: SYNC - A bidirectional synchronization signal used to coordinate the switching frequency of multiple units. Synchronization may be achieved by connecting the SYNC signal of each unit together or by using an external master clock signal. The oscillator timing capacitor, CT, is always required regardless of the synchronization method used. The paralleled unit with the highest oscillator frequency assumes control. Self- synchronization is not recommended for oscillator frequencies above 900kHz. For higher switching frequencies, an external clock with a pulse width less than one-half of the oscillator period must be used. RTC - This is the oscillator timing capacitor charge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the charge current. The charge current is nominally twice this current. The PWM maximum ON time is determined by the timing capacitor charge duration. RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 50x this current. The PWM deadtime is determined by the timing capacitor discharge duration. CT - The oscillator timing capacitor is connected between this pin and GND. VERROR - The inverting input of the PWM comparator. The error voltage is applied to this pin to control the duty cycle. Increasing the signal level increases the duty cycle. The node may be driven with an external error amplifier or opto-coupler. Typical Performance Curves FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE FIGURE 2. OSCILLATOR CT DISCHARGE CURRENT GAIN FIGURE 3. DEADTIME (TD) vs CAPACITANCE FIGURE 4. CAPACITANCE vs FREQUENCY 1.001 1.000 0.999 0.998 0.997 -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 65 60 55 50 45 40 0 50 100 150 200 250 300 350 400 450 500 RTD CURRENT (µA) 1•104 1•103 100 10 10 20 30 40 50 60 70 80 90 100 RTD (k Ω) 470 330 220 100 CT (pF) = 680 1000 1•106 1•104 60 70 80 90 100 RTC (k Ω) 10 20 30 40 50 680 1000 330 470 220 100 CT (pF) = RTD = 10k 1•105 IOUT 2QfSW • • = A (EQ. 1) |
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