8

FN6487.1

August 23, 2007

VSW - This is the switched regulated low voltage output

supply derived from VIO. Bypass to GND with a 1.0

μF

capacitor. Its output is adjustable from 0V to 15.0V using an

appropriate divider from VCONT to VADJ and GND. VSW is

nominally 7 x VSWADJ. Protection circuitry prevents the

output from exceeding 23V in the event of a fault on

VSWADJ (short high). The minimum output current

capability is 50mA with transient capability to > 80mA. VSW

may be soft-started by placing a capacitor from VSWADJ to

GND.

ENABLE - The positive logic on/off control input that

controls the VSW output. A logic high enables VSW.

VSWCOMP - A 220pF compensating capacitor is placed

between VSWCOMP and VSW to stabilize the control loop.

This value may vary depending on the output load and

capacitance applied between VSW and GND.

VSWADJ - The feedback adjustment pin for VSW. A divider

from VCONT to GND sets the output voltage for VSW.

VSWADJ has a node discharge device that activates

momentarily at power-up, when disabled (ENABLE low), and

during power-down sequences. VSW is nominally

7 x VSWADJ.

Functional Description

Features

The control circuitry used in Telecom/Datacom DC/DC

converters often requires an operating bias voltage

significantly lower than the source voltage available to the

converter. Many applications use a discrete linear regulator

from the input source to create the bias supply. Often an

auxiliary winding from the power transformer is used to

supplement or replace the linear supply once the converter

is operating. The auxiliary winding bias voltage may require

regulation, as well, to minimize the voltage variation inherent

in unregulated transformer winding outputs. When

implemented discretely, this circuitry occupies significant

PWB area, a considerable problem in today’s high density

converters.

The ISL6720A triple linear regulator simplifies the start-up

and operating bias circuitry needed in Telecom and Datacom

DC/DC converters by integrating these functions, and more,

in a small 4mmx4mm DFN package.

VIO

VIO is the primary output of the ISL6720A, providing bias

voltage whenever the input source voltage, VPWR, is above

its under voltage lockout (UVLO) threshold. VIO, which is an

abbreviation for “voltage input/output”, is adjustable from

0.5V to 20V using the VADJ input, and may be back-biased

up to 40V from an external source independent of VPWR.

The back-bias voltage must be higher than the VIO setpoint

to disable the internal VIO regulator. The transition from

internal VIO to external VIO is not abrupt. As the back-bias

voltage increases above the VIO setpoint, the load current

on VIO gradually transfers from the VIO regulator to external

back-bias source. Depending on load, the back-bias voltage

may have to exceed the VIO setpoint by as much as 3V

before the VIO regulator is off.

The output voltage of VIO is set by applying a reference

voltage to VADJ. The reference voltage may be set by using

a resistor and zener diode combination from the VPWR

input. VIO ranges from 0.5V to 4.5V below the voltage

applied to VADJ depending on the load on VIO. VIO can

source more than 125mA for short durations, limited only by

the device power dissipation and the thermal constraints of

the application.

VIO may be soft-started using the VADJ input. By limiting the

rate of rise of VADJ, the risetime of VIO may be controlled.

Soft-start may be accomplished by placing a capacitor to

ground from VADJ. The capacitor to ground and the resistor

from VPWR determine the RC charging characteristic for the

voltage at VADJ. Since VADJ is pulled low at power-up and

power-down, soft-start always starts from a known state.

The soft-start rate cannot exceed the intrinsic risetime set by

the current limit threshold of the output. As load capacitance

increases, the intrinsic risetime increases. In general,

placing large capacitance values on VIO should be avoided,

particularly if the source voltage applied to VPWR is high.

Having a large load capacitance and high input voltage

results in high power dissipation for a longer duration and

may activate the over-temperature protection before VIO

can be biased externally. Under such conditions, steady

state operation would not be achievable.

If the auxiliary transformer winding used to back-bias VIO

requires a large value of capacitance, it can be isolated from

VIO using a diode as shown in Figure 6.

VIO

VADJ

V

OFFSET

–

=

V

(EQ. 1)

FIGURE 5. SETPOINT ADJUSTMENT FOR VIO

1

VADJ

VPWR

ENABLE

VSW

VIO

2

7

9

10

11

3

4

8

VCONT

VSWCOMP

GND

VSWADJ

56

VCOMP

N/C

VIN

ISL6720A