ISL6551

9

FN9066.6

April 30, 2015

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Drive Signals Timing Diagrams

Timing Diagram Descriptions

The two upper drivers (UPPER1 and UPPER2) are driven at a

fixed 50% duty cycle and the two lower drivers (LOWER1 and

LOWER2) are PWM controlled on the trailing edge, while the

leading edge employs resonant delay (t2 and t4). In current

Blanking (LEB) circuits and then compared to a control signal

(EAO). Spikes, due to parasitic elements in the bridge circuit,

would falsely trigger the comparator generating the PWM

signal. To prevent false triggering, the leading edge of the

sensed current signal is blanked out by t1, which can be

programmed at the R_LEB pin with a resistor. Internal switches

gate the analog input to the PWM comparator, implementing

the blanking function that eliminates response degrading delays

which would be caused if filtering of the current feedback was

incorporated. The dead time (t3 and t5) is the delay to turn on

the upper FET (UPPER1/UPPER2) after its corresponding lower

FET (LOWER1/LOWER2) is turned off when the bridge is

operating at maximum duty cycle in normal conditions, or is

responding to load transients or input line dipping conditions.

Therefore, the upper and lower FETs that are located at the

same side of the bridge can never be turned on together, which

eliminates shoot-through currents. SYNC1 and SYNC2 are the

gate control signals for the output synchronous rectifiers. They are

biased by VDD and are capable of driving capacitive loads up to

20pF at 1MHz clock frequency (500kHz switching frequency).

External drivers with high current capabilities are required to drive

the synchronous rectifiers, cascading with both synchronous

signals (SYNC1 and SYNC2).

CLOCK

UPPER1

UPPER2

SYNC1

SYNC2

LOWER1

RAMP ADJUST

OUTPUT TO

PWM

LOGIC

T1

T2

T3

T4

T5

t1 = Leading edge blanking

t2 = t4 = Resonant delay

t3 = t5 = dead time

In the above figure, the values for t1 through t5 are exaggerated for demonstration purposes.

LOWER2

NOTES:

EAO

EAO

EAO

FIGURE 2. DRIVE SIGNALS TIMING DIAGRAMS