9

FN6412.1

April 10, 2007

Functional Description

The ISL6423B single output voltage regulator makes an

ideal choice for advanced satellite set-top box and personal

video recorder applications. The device utilizes built-in

DC/DC step up converters that, operates from a single

supply source ranging from 8V to 14V, and generates the

voltage needed to enable the linear post-regulator to work

with a minimum of dissipated power. An undervoltage

lockout circuit disables the device when VCC drops below a

fixed threshold (7.5V typ).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of

22kHz in accordance with DiSEqC (EUTELSAT) standards.

No further adjustment is required. The tone oscillator can be

dedicated pin (EXTM) that allows immediate DiSEqC data

encoding separately for each LNB. All the functions of this IC

registers. The same registers can be read back, and four bits

will report the diagnostic status. The internal oscillator

operates the converters at twenty times the 22k tone

supports 2.5V, 3.3V or 5V logic, up to an operational speed of

400kHz.

If the Tone Enable (ENT) bit is set LOW and the MSEL bits

internal tone signal, modulating the DC output with a

of this signal usually provides the LNB with information

about the band to be received.

Burst coding of the tone can be accomplished due to the fast

response of the EXTM input and rapid tone response. This

allows implementation of the DiSEqC (EUTELSAT)

protocols.

When the ENT bit is set HIGH, a continuous 22kHz tone is

generated regardless of the EXTM pin logic status for the

regulator channel LNB-A. The ENT bit must be set LOW

when the EXTM pin is used for DiSEqC encoding.

The EXTM accepts an externally modulated tone command

DiSEqC Decoder

TDIN is the input to the tone decoder. It accepts and the tone

capacitor. The detector threshold can be set to 200mV max

in the Receive mode and to 400mV min in the Transmit

mode by means of the logic presented to the TXT pin. If tone

is detected the open drain pin TDOUT is asserted low. This

enables the tone diagnostics to be performed, apart from the

normal tone detection function.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.75

μF. In order to minimize the power

dissipation, the output voltage of the internal step-up

converter is adjusted to allow the linear regulator to work at

minimum dropout.

When the device is put in the shutdown mode (EN = LOW),

the PWM power block is disabled. When the regulator blocks

are active (EN = HIGH and VSPEN = LOW), the output can

(typical) by means of the VTOP and VBOT bits (Voltage

Select) for remote controlling of non-DiSEqC LNBs.

When the regulator blocks are active (EN = HIGH and

VSPEN = HIGH), the VBOT and SELVTOP pin will control

the output between 13V and 14V and the VTOP and

SELVTOP pin will control the output between 18V and 19V.

Output Timing

The output voltage rise and fall times can be set by an the

external capacitor on the TCAP pin. The output rise and fall

times is given by the equation:

Where C is the TCAP value in nF, T is the required transition

time in ms and

ΔV is the differential transition voltage from

low output voltage range to the high output range in Volts.

The maximum recommended value for TCAP is 0.15µF. Too

large a value of TCAP prevents the output from rising to the

nominal value, within the soft-start time when the error

amplifier is released. Too small a value of the TCAP can cause

high peak currents in the boost circuit. For example, a 10V/ms

slew on a 80µF VSW capacitor with an inductor of 15µH can

cause a peak inductor current of approximately 2.3A.

Current Limiting

Dynamic current limiting block has four thresholds that can

be selected by the ISEL H and ISEL L bits of the SR. Refer

to Table 8 and Table 9 for threshold selection using these

bits. The DCL bit has to be set to low for this mode of

operation. In the dynamic overcurrent mode a fault

exceeding the selected overcurrent threshold for a period

greater than 51ms, will shutdown the output for 900ms,

the OLF bit is returned to the low state, a soft-start cycle

the fault is still present the overcurrent will be reached early

in the soft-start cycle and the 51ms shutdown timer will be

started again. If the fault is still present at the end of the

51ms, the OLF bit is again set high and the device once

again enters the 900ms OFF time. This dynamic operation

greatly reduces the power dissipation in a short circuit

condition, while still ensuring excellent power-on start-up in

most conditions.

C

327.6T

ΔV

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(EQ. 1)