TMS320C6674_15 datasheet(3/238 Pages) TI

Part #	TMS320C6674

Description	Multicore Fixed and Floating-Point Digital Signal Processor

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Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6674 Features and Description

3

SPRS692E—March 2014

TMS320C6674

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For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition,

the C66x core integrates floating point capability and the per-core raw computational performance in an

industry-leading 40 GMACS/core and 20 GFLOPS/core (@1.25 GHz operating frequency). It can execute 8

single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations,

and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted

for floating point and vector math oriented processing. These enhancements yield sizeable performance

improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions.

The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP

cores, ensuring software portability and shortened software development cycles for applications migrating to faster

hardware.

The C6674 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache,

there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also

integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All

L2 memories incorporate error detection and error correction. For fast access to external memory, this device

includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.

This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and

Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I

2C, UART, Telecom Serial Interface Port

(TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication

between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding

to the network awareness of this device is a network co-processor that includes both packet and optional security

acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for

the entire multicore C6674 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities.

The C6674 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source

code execution.

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