 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ISL6363CRTZ Datasheet(PDF) 11 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
ISL6363CRTZ Datasheet(HTML) 11 Page - Intersil Corporation |
|
|
11 / 32 page  ISL6363 11 FN6898.1 September 5, 2013 Gate Driver Timing Diagram Theory of Operation Multiphase R3 Modulator The ISL6363 is a multiphase regulator implementing Intel’s™ VR12™ protocol. It has two voltage regulators, VR1 and VR2, on one chip. VR1 can be programmed for 1, 2, 3, or 4-phase operation, and VR2 is dedicated for 1-phase operation. The following description is based on VR1, but also applies to VR2 because the same architecture is implemented. The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator) modulator. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 3 conceptually shows the multiphase R3 modulator circuit, and Figure 4 shows the operation principles. A current source flows from the VW pin to the COMP pin, creating a voltage window set by the resistor between the two pins. This voltage window is called VW window in the following discussion. Inside the IC, the modulator uses the master clock circuit to generate the clocks for the slave circuits. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth waveform traversing between the VW and COMP voltages. It resets to VW when it hits COMP, and generates a one-shot master clock signal. A phase sequencer distributes the master clock signal to the slave circuits. If VR1 is in 4-phase mode, the master clock signal will be distributed to the four phases, and the Clock1~4 signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the master clock signal will be distributed to the three phases, and the Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase mode, the master clock signal will be distributed to Phases 1 and 2, and the Clock1 and Clock2 signals will be 180° out-of-phase. If VR1 is in 1-phase mode, the master clock signal will be distributed to Phase 1 only and be the Clock1 signal. Each slave circuit has its own ripple capacitor Crs, whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source charges Crs. When Crs voltage VCrs hits VW, the slave circuit turns off the PWM pulse, and the current source discharges Crs. PWM UGATE LGATE 1V 1V tUGFLGR tRL tFU tRU tFL tLGFUGR FIGURE 3. R3 MODULATOR CIRCUIT Crm gmVo MASTER CLOCK VW COMP MASTER CLOCK Phase Sequencer Clock1 Clock2 R IL1 gm Clock1 Phase1 Crs1 VW S Q PWM1 L1 R IL2 gm Clock2 Phase2 Crs2 VW S Q PWM2 L2 Co Vo Vcrm Vcrs1 Vcrs2 MASTER CLOCK CIRCUIT SLAVE CIRCUIT 1 SLAVE CIRCUIT 2 R IL3 gm Clock3 Phase3 Crs3 VW S Q PWM3 L3 Vcrs3 SLAVE CIRCUIT 3 Clock3 |
Similar Part No. - ISL6363CRTZ |
|
Similar Description - ISL6363CRTZ |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
