SW

Ramp

Generator

Oscillator

Current

Sensor

EN

PGND

C4

L1

+

EA

R2

C2

VIN

PWM Control

COMP

R1

R3

R4

C3

SS

FREQ

SYNC

FB

FB

Gate

Driver

C1

AGND

D1

1.229 V

Reference

TPS61175-Q1

SLVSCN9 – DECEMBER 2014

www.ti.com

8 Detailed Description

8.1 Overview

The TPS61175-Q1 integrates a 40-V low side switch FET for up to 38-V output. The device regulates the output

with current mode PWM (pulse width modulation) control. The PWM control circuitry turns on the switch at the

beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as

inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output

capacitor. When the inductor current rises to the threshold set by the error amplifier output, the power switch

turns off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the

output capacitor and supply the load current. This operation repeats each every switching cycle. As shown in the

block diagram, the duty cycle of the converter is determined by the PWM control comparator which compares the

error amplifier output and the current signal. The switching frequency is programmed by the external resistor or

synchronized to an external clock signal.

A ramp signal from the oscillator is added to the current ramp to provide slope compensation. Slope

compensation is necessary to avoid subharmonic oscillation that is intrinsic to the current mode control at duty

cycle higher than 50%. If the inductor value is lower than 4.7

μH, the slope compensation may not be adequate.

The feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The

output of the error amplifier is connected to the COMP pin. An external RC compensation network is connected

to the COMP pin to optimize the feedback loop for stability and transient response.

8.2 Functional Block Diagram

8

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