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TPS55332-Q1 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS55332-Q1 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 36 page ( ) Vout Vref R8 R7 R8 tol = tol + tol + tol R8+R7 æ ö ´ ç ÷ è ø R8 Vout = Vref 1 + (Volts) R7 æ ö ç ÷ è ø TPS55332-Q1 www.ti.com SLVS939B – JUNE 2009 – REVISED DECEMBER 2014 7.3 Feature Description The TPS55332 is a step up (boost) dc/dc converter using voltage-control mode scheme. The following sections include descriptions of the individual pin functions. 7.3.1 Input Voltage (VIN) The VIN pin is the input power source for the TPS55332. This pin must be externally protected against voltage level transients greater than 60 V and reverse battery. In boost mode the input current drawn from this pin is pulsed, with fast rise and fall times. Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an input filter inductor may also be required. 7.3.2 Output Voltage (Vout) The output voltage, Vout, is generated by the converter supplied from the battery voltage VIN and external components (L, C). The output is sensed through an external resistor divider and compared with an internal reference voltage. The value of the adjustable output voltage in boost mode is selectable between VIN × 1.05 to 50 V if the minimum ON time (ton) and minimum OFF times are NOT violated by choosing the external resistors, according to the following relationship: (1) Where: R7 and R8 are feedback resistors Vref = 2.5 V (typ) The internal reference voltage Vref has a ±1.5% tolerance. The overall output voltage tolerance is dependent on the external feedback resistors. To determine the overall output voltage tolerance, use the following relationship: (2) Typically, an output capacitor within the range of 10 μF to 400 μF is used. This terminal has a filter capacitor with low ESR characteristics in order to minimize output ripple voltage. 7.3.3 Regulated Supply Voltage (VReg) There is an integrated forward biased diode between VReg and VIN. VReg is tied to Vout and used to bias VIN when Vout > Vsupply. 7.3.4 Over-Current Protection (SW) Over-current protection is implemented by sensing the current through the NMOS switch FET. The sensed current is then compared to a current reference level representing the over-current threshold limit. If the sensed current exceeds the over-current threshold limit, the over-current indicator is set true. The system ignores the over-current indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. Once the over-current indicator is set true, over-current protection is triggered. The MOSFET is turned off for the rest of the cycle after a propagation delay. The over-current protection scheme is called cycle-by-cycle current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature of the device starts to rise, and the TSD kicks in and shuts down switching until the device cools down. 7.3.5 Oscillator Frequency (RT) The oscillator frequency is selectable by means of a resistor placed at the RT pin. The switching frequency (ƒsw) can be set in the range of 80 kHz to 2.2 MHz. In addition, the switching frequency can be imposed externally by a clock signal (ƒext) at the SYNC pin with ƒsw < ƒext < 2 × ƒsw. In this case the external clock overrides the switching frequency determined by the RT pin, and the internal oscillator is clocked by the external synchronization clock input. Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS55332-Q1 |
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