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ISL6141IB Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6141IB Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 19 page 5 . Absolute Maximum Ratings Thermal Information Supply Voltage (VDD to VEE). . . . . . . . . . . . . . . . . . . . -0.3V to 100V DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . . -0.3V to 100V UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40oC to 85oC Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0oC to 70oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . 36V to 72V Thermal Resistance (Typical, Note 1) θJA (oC/W) 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. PWRGD is referenced to DRAIN; VPWRGD-VDRAIN = 0V. Electrical Specifications VDD = +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either Commercial (0oC to 70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX Units DC PARAMETERS VDD PIN Supply Operating Range VDD 20 - 80 V Supply Current IDD UV = 3V; OV = VEE; SENSE = VEE; VDD = 80V 2.4 4.5 mA UVLO High VUVLOH VDD Low to High transition 15 16.7 19 V UVLO Low VUVLOL VDD High to Low transition 13 14.8 17 V UVLO hysteresis 1.9 V GATE PIN GATE Pin Pull-Up Current IPU GATE Drive on, VGATE = VEE -30 -50 -60 µA GATE Pin Pull-Down Current IPD1 GATE Drive off, UV or OV false 70 mA GATE Pin Pull-Down Current IPD2 GATE Drive off, Over-Current Time-Out 70 mA GATE Pin Pull-Down Current IPD3 GATE Drive off; Hard Fault (Vsense > 210mV) 350 mA External GATE Drive (VDD = 20V, 80V) ∆ V GATE (VGATE - VEE), 20V <=VDD <=80V 12 13.6 15 V GATE High Threshold (PWRGD/PWRGD active) VGH ∆VGATE - VGATE 2.5 V SENSE PIN Current Limit Trip Voltage VCL VCL = (VSENSE - VEE)40 50 60 mV Hard Fault Trip Voltage VHFT VHFTV = (VSENSE - VEE) 210 mV SENSE Pin Current ISENSE VSENSE = 50mV -1.3 -4.0 µA UV PIN UV Pin High Threshold Voltage VUVH UV Low to High Transition 1.240 1.255 1.270 V UV Pin Low Threshold Voltage VUVL UV High to Low Transition 1.105 1.120 1.145 V UV Pin Hysteresis VUVHY 135 mV ISL6141, ISL6151 |
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