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DAC5689 Datasheet(PDF) 3 Page - Texas Instruments |
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DAC5689 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 50 page  DAC5689 www.ti.com SLLS989A – SEPTEMBER 2009 – REVISED AUGUST 2010 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. 51, 54, 55, AVDD I Analog supply voltage. (3.3V) 59, 62 BIASJ 57 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND. CLK2 2 I Positive DAC clock input. Accepts frequencies up to 800MHz. CLK2C 3 I Complementary CLK2 input. In Dual Clock Mode can be used to provide the lower frequency input clock. The lower frequency clock can be differential or single-ended. If single-ended CLK1 can be used as the clock input. CLKO_CLK1 25 I/O CLK1C must be AC coupled to GND in this case. Optionally provides (CLKO) output for data bus source. Internal pull-down. In Dual Clock Mode can be used to provide the lower frequency input clock. The lower frequency clock can be differential or single-ended. If differential, CLK1C is the complementary clock input. If CLK1C 26 I/O single-ended it can be used as the clock input. CLKO_CLK1 must be AC coupled to GND in this case. Internal pull-down. Internal clock buffer supply voltage. (1.8V) CLKVDD 1 I It is recommended to isolate this supply from DVDD. A-Channel Data Bits 0 through 15. DA15 is most significant data bit (MSB) – pin 7 DA[15..0] 7, 8, 11–24 I DA0 is least significant data bit (LSB) – pin 24 Internal pull-down. The order of bus can be reversed via CONFIG4 reva bit. B-Channel Data Bits 0 through 15. DB15 is most significant data bit (MSB) – pin 43 40–43, DB[15..0] I 27–38 DB0 is least significant data bit (LSB) – pin 27 Internal pull-down. The order of bus can be reversed via CONFIG4 revb bit. Digital supply voltage. (1.8V) 10, 39, 50, DVDD I 63 For best performance it is recommended to isolate pins 10 and 39 from all other 1.8V supplies. Used as external reference input when internal reference is disabled (i.e., EXTLO connected to EXTIO 56 I/O AVDD). Used as internal reference output when EXTLO = GND, requires a 0.1mF decoupling capacitor to GND when used as reference output EXTLO 58 O Connect to GND for internal reference, or AVDD for external reference. 4, Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD GND I Thermal and IOVDD supplies. Pad A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data IOUTA1 52 O input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear on the IOUTA1/A2 pair only. A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA2 53 O IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOUTB1 61 O B-Channel DAC current output. Refer to IOUTA1 description above. IOUTB2 60 O B-Channel DAC complementary current output. Refer to IOUTA2 description above. 3.3V supply voltage for all digital I/O. Note: This supply input should remain at 3.3V regardless of the IOVDD 9 I 1.8V or 3.3V selectable digital input switching thresholds via CONFIG26 io_1p8_3p3. NC 64 I No connect. Leave open for proper operation. SYNC 5 I Optional SYNC input for internal clock dividers, FIFO, NCO and QMC blocks. Internal pull-down. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5689. Internal pull-up. Bi-directional serial data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO SDIO 46 I/O pin is an input only. Internal pull-down. Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is 3-stated in 3-pin SDO 45 O interface mode (default). Internal pull-down. Transmit enable input. Internal pull-down. TXENABLE must be high for the DATA to the DAC to be TXENABLE 6 I enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): DAC5689 |
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