CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs

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3

Note 1: Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.

Note 2: Sample tested at +25°C to ensure compliance.

Note 3: Accuracy may degrade at conversion times other than those specified.

Note 4: Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:

For MX7575

CS = RD = BUSY = high;

For MX7576

CS = RD = BUSY = MODE = high.

Using recommended

clock components:

LSB

±1/4

Power-Supply Rejection

mW

15

Power Dissipation

mA

7

Supply Current

36

V

5

Supply Voltage

µs

10

30

Conversion Time with

Internal Clock

515

µs

10

Conversion Time with

External Clock

5

pF

10

Floating State Output

Capacitance (Note 2)

µA

±10

Floating State Leakage Current

V

2.4

Input High Voltage

V

0.8

Input Low Voltage

±1

V

4.0

Output High Voltage

V

0.4

Output Low Voltage

700

µA

800

Input Low Current

700

µA

800

Input High Current

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

MX757_S/T

MX757_J/A/K/B

±5% for specified performance

MX7576

MX7575

MX757_J/A/K/B

MX757_S/T

MX757_J/A/K/B

D0–D7

MX757_S/T

CONDITIONS

ELECTRICAL CHARACTERISTICS (continued)

CLOCK

LOGIC OUTPUTS (D0–D7,

BUSY)

CONVERSION TIME (Note 3)

POWER REQUIREMENTS (Note 4)