Dual ECL and Dual/Quad PECL, 500ps,

Ultra-High-Speed Comparators

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11

Timing Information (MAX9600/MAX9601)

The timing diagram (Figure 1) illustrates the operation

of a comparator with latch enable. The top line of the

diagram illustrates a latch-enable pulse. Initially, the

latch-enable input (LE, LE_) is differentially high, which

places the comparator in latch mode. When the input

signal (IN_+, IN_-) switches from low to high, the output

(Q_, Q_) remains latched to the previous low state.

When the latch-enable input goes differentially low,

starting the compare function, the output responds to

leading edges of the subsequent input signal switch

ing on the direction of the input transitions) until a high

latch-enable pulse places the device in latch mode

again. The input signal must occur at minimum time

proper latch operation.

ECL/PCL

The MAX9600/MAX9601/MAX9602 outputs are emitter

followers that require external resistive connections to a

for proper static and dynamic operation. When properly

MAX9602). Output-current polarity always sinks into the

termination scheme during proper operation.

ECL-output signal levels are referenced to GND, and

Chip Information

MAX9600 TRANSISTOR COUNT: 558

MAX9601 TRANSISTOR COUNT: 600

MAX9602 TRANSISTOR COUNT: 608

PROCESS: Bipolar

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

QB

QB

LEB

LEA

QA

QA

LEB

HYSB

HYSA

LEA

12

11

9

10

INB-

INB+

INA+

INA-

MAX9601

TSSOP-20

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

QA

QA

INB+

INA-

INA+

QB

QB

QC

INC-

INC+

INB-

16

15

14

13

9

10

11

12

QC

QD

QD

IND-

IND+

TSSOP-24

MAX9602

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

QB

QB

GND

LEB

LEA

GND

QA

QA

TOP VIEW

LEB

HYSB

HYSA

LEA

12

11

9

10

INB-

INB+

INA+

INA-

MAX9600

TSSOP-20

Pin Configurations