Ensure that the output currents do not exceed the con-

tinuous safe output current limit or surge output current

limit as specified in the Absolute Maximum Ratings

table. Under all operating conditions, the device’s total

thermal limits should be observed.

Supply Bypassing

ceramic 0.1µF and 0.01µF capacitors in parallel and as

close to the device as possible, with the 0.01µF capaci-

tor closest to the device. Use multiple parallel vias to

minimize parasitic inductance.

PC Board Traces

Input and output trace characteristics affect the perfor-

mance of the MAX9370/MAX9371/MAX9372. Connect

each differential output to a 50

Ω characteristic impedance

trace. Minimize the number of vias to prevent impedance

discontinuities. Reduce reflections by maintaining the 50

Ω

characteristic impedance through connectors and across

cables. Reduce skew within a differential pair by match-

ing the electrical length of the traces.

Chip Information

TRANSISTOR COUNT: 358

PROCESS: Bipolar

LVTTL/TTL-to-Differential LVPECL/PECL

Translators

6

_______________________________________________________________________________________

D_

0V (DIFFERENTIAL)

20%

80%

20%

80%

Q_

Q_

Q_ - Q_

50%

50%

Figure 1. Input-to-Output Propagation Delay and Transition Timing Diagram