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MAX9160EUI Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX9160EUI Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 13 page LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver 8 _______________________________________________________________________________________ Propagation Delay and RSET The MAX9160 delay can be adjusted by connecting a resistor from RSET to ground. See Typical Operating Characteristics for a graph of delay vs. RSET. Output Enables Each bank of seven LVTTL/LVCMOS drivers is con- trolled by an output enable. Outputs follow the selected input when EN_ is high. Outputs are low (not high impedance) when EN_ = low. Power Dissipation and Package Type Power dissipation at high switching frequencies may exceed the power dissipation capacity of the standard TSSOP package (see the Supply Current vs. Frequency graph in the Typical Operating Characteristics). An EP version of the TSSOP package is available that dissi- pates higher power. Also, a space-saving QFN pack- age with EP is available. The EP must be soldered to the PC board. Supply Bypassing Bypass each supply pin with high-frequency surface- mount ceramic 0.1µF and 0.001µF capacitors in paral- lel as close to the device as possible, with the smaller value capacitor closest to the device. Board Layout A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep input and output signals separated to prevent coupling. VCC/2 VCC/2 VCC SE_IN IN- IN+ OUT_ 20% VCC tPLH tPHL VOH VOL 0V DIFFERENTIAL 0V DIFFERENTIAL 0V 80% VCC 80% VCC 50% VCC tR tF 50% VCC 20% VCC Figure 3. Transition Time and Propagation Delay Timing Diagram Chip Information TRANSISTOR COUNT: 756 PROCESS: CMOS |
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