Fail-Safe

The fail-safe feature of the MAX9125/MAX9126 sets the

output high when:

• Inputs are open.

• Inputs are undriven and shorted.

• Inputs are undriven and terminated.

A fail-safe circuit is important because under these

conditions, noise at the inputs may switch the receiver

and it may appear to the system that data is being

received. Open or undriven terminated input conditions

can occur when a cable is disconnected or cut, or

when the LVDS driver outputs are high impedance. A

short condition can occur because of a cable failure.

The fail-safe input network (Figure 1) samples the input

(nominal). When the input is driven to levels specified in

the LVDS standards, the input common-mode voltage

activated. If the inputs are open or if the inputs are

undriven and shorted or undriven and parallel terminat-

ed, there is no input current. In this case, a pullup resis-

0.3V, activating the fail-safe circuit and forcing the out-

put high.

Applications Information

Power-Supply Bypassing

ceramic 0.1µF and 0.001µF capacitors in parallel, as

close to the device as possible, with the smaller valued

Differential Traces

Input trace characteristics affect the performance of the

MAX9125/MAX9126. Use controlled-impedance PC

board traces to match the cable characteristic imped-

ance. The termination resistor is also matched to this

characteristic impedance.

Eliminate reflections and ensure that noise couples as

common mode by running the differential traces close

together. Reduce skew by matching the electrical

length of the traces. Excessive skew can result in a

degradation of magnetic field cancellation.

Each channel’s differential signals should be routed

close to each other to cancel their external magnetic

field. Maintain a constant distance between the differ-

ential traces to avoid discontinuities in differential

impedance. Avoid 90° turns and vias to further prevent

impedance discontinuities.

Cables and Connectors

Transmission media typically have a controlled differen-

tial impedance of 100

Ω. Use cables and connectors

Quad LVDS Line Receivers with

Integrated Termination

8

_______________________________________________________________________________________

1.5V

EN WHEN EN = GND

OUTPUT WHEN

OUTPUT WHEN

1.5V

1.5V

0.5V

0.5V

1.5V

3V

0

3V

GND

0

50%

50%

Figure 5. High-Z Delay Waveforms