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DRV8701PRGER Datasheet(PDF) 8 Page - Texas Instruments |
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DRV8701PRGER Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 42 page  DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RIDRIVE < 1 kΩ to GND 12.5 RIDRIVE = 33 kΩ ±5% to GND 25 RIDRIVE = 200 kΩ ±5% to GND, or IDRIVE,SNK Peak sink current 50 mA RIDRIVE < 1 kΩ to AVDD RIDRIVE > 500 ±5% kΩ to GND 200 RIDRIVE = 68 kΩ ±5% to AVDD 300 Source current after tDRIVE 6 IHOLD FET holding current mA Sink current after tDRIVE 25 GHx 490 ISTRONG FET hold-off strong pulldown mA GLx 690 Pulldown GHx to SHx 200 ROFF FET gate hold-off resistor k Ω Pulldown GLx to GND 150 CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF) VVREF VREF input voltage For current internal chopping 0.3(2) AVDD V 50 < VSP < 200 mV; VSN = GND 18 20 22 AV Amplifier gain V/V 10 < VSP < 50 mV; VSN = GND 16 20 24 VOFF SO offset VSP = VSN = GND 50 250 mV ISP SP input current VSP = 100 mV; VSN = GND -40 μA VSP = VSN = GND to tSET (3) Settling time to ±1% 1.5 µs VSP = 100 mV, VSN = GND CSO (3) Allowable SO pin capacitance 1 nF tOFF PWM current regulation off-time 25 µs tBLANK PWM blanking time 2 µs PROTECTION CIRCUITS VM falling; UVLO report 5.4 5.8 VUVLO VM undervoltage lockout V VM rising; UVLO recovery 5.6 5.9 VUVLO,HYS VM undervoltage hysteresis Rising to falling threshold 100 mV tUVLO VM UVLO falling deglitch time VM falling; UVLO report 10 μs VCPUV Charge pump undervoltage CPUV report VM + 2.8 V Overcurrent protection trip level, High-side FETs: VM – SHx VDS OCP 0.8 1 V VDS of each external FET Low-side FETs: SHx – SP Overcurrent protection trip level, VSP OCP VSP voltage with respect to GND 0.8 1 V measured by sense amplifier tOCP Overcurrent deglitch time 4.5 µs tRETRY Overcurrent retry time 3 ms TTSD (3) Thermal shutdown temperature Die temperature, TJ 150 °C THYS (3) Thermal shutdown hysteresis Die temperature, TJ 20 °C Positive clamping voltage 10.5 13 VGS CLAMP Gate drive clamping voltage V Negative clamping voltage –1 –0.7 –0.5 (2) Operational at VREF = 0 to 0.3 V, but accuracy is degraded (3) Specified by design and characterization data 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 |
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