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MAX809REXR-T10 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX809REXR-T10 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 8 page _______________________________________________________________________________________ 5 Detailed Description A microprocessor’s (µP’s) reset input starts the µP in a known state. The MAX803/MAX809/MAX810 assert reset to prevent code-execution errors during power- up, power-down, or brownout conditions. They assert a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset thresh- old. The MAX803 uses an open-drain output, and the MAX809/MAX810 have a push-pull output stage. Connect a pull-up resistor on the MAX803’s RESET out- put to any supply between 0 and 6V. Applications Information Negative-Going VCC Transients In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the MAX803/ MAX809/MAX810 are relatively immune to short-duration negative-going VCC transients (glitches). Figure 1 shows typical transient duration vs. reset com- parator overdrive, for which the MAX803/MAX809/ MAX810 do not generate a reset pulse. The graph was generated using a negative-going pulse applied to VCC, starting 0.5V above the actual reset threshold and end- ing below it by the magnitude indicated (reset compara- tor overdrive). The graph indicates the maximum pulse width a negative-going VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, for the MAX8__L and MAX8__M, a VCC transient that goes 100mV below the reset threshold and lasts 20µs or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity. Ensuring a Valid Reset Output Down to VCC = 0 When VCC falls below 1V, the MAX809 RESET output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS logic inputs con- nected to RESET can drift to undetermined voltages. This presents no problem in most applications since most µP and other circuitry is inoperative with VCC below 1V. However, in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any stray leakage currents to flow to 3-Pin Microprocessor Reset Circuits R1 100k VCC GND MAX809 RESET Figure 2. RESET Valid to VCC = Ground Circuit 2 RESET (MAX803/ MAX809) RESET Output remains low while VCC is below the reset threshold, and for at least 140ms after VCC rises above the reset threshold. 1 GND Ground PIN NAME FUNCTION RESET (MAX810) RESET Output remains high while VCC is below the reset threshold, and for at least 140ms after VCC rises above the reset threshold. _____________________Pin Description 400 320 0 1 100 1000 160 80 240 RESET COMPARATOR OVERDRIVE, VTH - VCC (mV) 10 TA = +25°C MAX8_ _J/L/M MAX8_ _R/S/T/Z Figure 1. Maximum Transient Duration Without Causing a Reset Pulse vs. Reset Comparator Overdrive 3 VCC Supply Voltage (+5V, +3.3V, +3.0V, or +2.5V) |
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