LSB

MSB

CS

CK

Register

Parallel Output

Parallel Input

/16

Parallel Output

Serial input

Serial Output

Parallel Input

Parallel Output

CK

/16

Shift Register

(16 bits)

DOUT

MSB First

Parallel Input

EN

LSB

MSB

Output Latch

(Transparent if EN = High)

Internal

Diagnosis Register

DIN

MSB First

SCK

DRV3211-Q1

SLVSBS4 – DECEMBER 2012

www.ti.com

SERIAL PORT I/F

Description

The SPI is used to receive an input byte from CPU and to transmit an output byte to CPU. Four signals are

utilized according to the timing chart of Figure 4.

Figure 4. Block Diagram of SPI

•

CS – Chip Select

–

This input signal is utilized to select this IC by CPU.

–

This input signal is normally high and the communication is possible only when it is forced low.

–

When this input signal falls, the communication between this IC and the CPU starts.

–

Transmitted data is latched and the DOUT pin comes out of high impedance.

–

When this input signal rises, the communication stops.

–

The DOUT pin goes into high impedance. Then, the internal input register updates with the received bits

(only if the clock pulse numbers are right and the key bit of the DIN signals is correct).

–

The next falling edge starts another communication.

–

–

The pin has an internal pullup.

•

SCK – Synchronization Serial Clock

–

This input signal is utilized to synchronize the communication by CPU.

–

It is normally high and the correct clock pulse number is 16.

–

At each falling edge, the CPU writes a new bit on the DIN input and this IC writes a new bit on the DOUT

pin. At each rising edge, this IC reads the new bit on the DIN pin and the CPU reads the new bit on the

DOUT pin.

–

The maximum clock frequency is 4 MHz.

–

The pin has an internal pullup.

space

8

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