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DRV3204-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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DRV3204-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 38 page  DRV3204-Q1 www.ti.com SLVSBT3B – MARCH 2013 – REVISED JULY 2013 FLTCFG (address 0x02): Fault Detection Configuration Register Bit Name Type Reset Description 7 FLGLATCH_EN RW 0 Fault-flag (FLTFLG*) latch enable 0: Fault events do not latch fault-flag register bits. 1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until cleared. 6:4 MTOCTH RW 000 Motor overcurrent detection threshold 000: 2 V 001: 2.5 V 010: 3 V 011: 3.5 V 100: 4 V Others: 2 V 3 RSVD R 0 Reserved 2 VCCUVTH RW 0 VCC undervoltage detection threshold 0: 4 V 1: 4.2 V 1:0 VBUVTH RW 00 VB undervoltage detection threshold 00: 4 V 01: 4.5 V 10: 5 V 11: 5.5 V FLTEN0 (address 0x04): FAULT Pin Enable Register 0 Bit Name Type Reset Description 7 FE_MTOC RW 1 FAULT pin enable of FLTFLG0 register bits. 0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 6 FE_VCCOC RW 1 1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 6 5 FE_VCCOV RW 1 4 FE_VDDOV RW 1 3 FE_CPOV RW 1 2 FE_CPUV RW 1 1 FE_VBOV RW 1 0 FE_VBUV RW 1 FLTEN1 (address 0x05): FAULT Pin Enable Register 1 Bit Name Type Reset Description 7:1 RSVD R 0000 000 Reserved 0 FE_TSD RW 1 FAULT pin enable of TSD flag bit 0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 6 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links :DRV3204-Q1 |
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