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DRV3202-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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DRV3202-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 39 page  Do not switch to RES LOW when the VCC LOW time is less than tRES. tRES tRES Ignore transient voltage falling Switch to NMI-LOW after tRES delay when VCC is lower than VNMIL VNMI+VHS VB VCC VSTN NMI (Internal signal) RES is HIGH after tON from NMI-HIGH if internal clock is not generated (In case of malfunction). RES signal should remain in low voltage (< -0.4 V) and in this case, controlled CPU should be in tRH RES is LOW at NMI-LOW. tON tRL tOFF tON Pwth RES PRN Detecting only rising edge of PRN signal WDEN Switch to RES LOW if PRN stays at a High or LOW level. RES is LOW at NMI-LOW. If WDEN is LOW (or OPEN), and there is abnormal PRN: RES is active. If WDEN is HIGH, and there is abnormal PRN: no operation. RES is HIGH after tON from of NMI-HIGH. VNMI tRES DRV3202-Q1 www.ti.com SLVSBJ4A – OCTOBER 2012 – REVISED DECEMBER 2012 NOTE: WDEN = High, VCC undervoltage condition sets RES = Low Figure 3. Watchdog Timing Chart WATCHDOG ELECTRICAL CHARACTERISTICS (1) VB = 12 V,TA = –40°C to 125°C (unless otherwise specified) PARAMETER(2) CONDITIONS MIN TYP MAX UNITS WATCHDOG VSTN Function start VCC voltage RES – 0.8 1.3 V tON Power-on time RES 32 40 48 ms tOFF Clock off reset time RES 64 80 96 ms tRL Reset pulse low time RES Refer to Figure 3 16 20 24 ms tRH Reset pulse high time RES 64 80 96 ms tRES Reset delay time RES 30 71.5 90 µs Pwth Pulse width PRN 200 – – ns (1) The watchdog function is disabled and the timing parameters are invalid when the WDEN is at a high level. (2) Specified by design Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DRV3202-Q1 |
Similar Part No. - DRV3202-Q1_15 |
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