+5V Microprocessor Supervisory Circuits

4

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ELECTRICAL CHARACTERISTICS (continued)

Power-down

Enable mode

Disable mode

CONDITIONS

µs

15

RESET to CE OUT Delay

3.5

CE OUT Input Threshold

V

0.8

V

2.7

CE OUT Output

Ω

40

150

CE IN to CE OUT Resistance

(Note 6)

µA

±0.005

±1

CE IN Leakage Current

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Note 3: “-” = battery-charging current, “+” = battery-discharging current.

Note 4: WDI is internally serviced within the watchdog timeout period if WDI is left unconnected.

Note 5: WDI input is designed to be driven by a three-stated output device. To float WDI, the “high-impedance mode” of the output

device must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device

must also be able to source and sink at least 200µA when active.

Note 7: The chip-enable propagation delay is measured from the 50% point at

CE IN to the 50% point at CE OUT.

Disable mode,

CE OUT = 0V

mA

0.1

0.75

2.0

CE OUT Short-Circuit Current

(Reset Active)

50

ns

38

CE IN to CE OUT Propagation

Delay (Note 7)

CHIP-ENABLE GATING (MAX818 only)