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MAX795CPA Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX795CPA Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 20 page 3.0V/3.3V Adjustable Microprocessor Supervisory Circuits 8 _______________________________________________________________________________________ _______________Detailed Description General Timing Characteristics The MAX793/MAX794/MAX795 are designed for 3.3V and 3V systems, and provide a number of supervisory functions (see the Selector Guide on the front page). Figures 1 and 2 show the typical timing relationships of the various outputs during power-up and power-down with typical VCC rise and fall times. Manual Reset Input (MAX793/MAX794) Many microprocessor-based products require manual- reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. On the MAX793/MAX794, a logic low on MR asserts reset. Reset remains asserted while MR is low, and for tRP (200ms) after it returns high. During the first half of the reset time- out period (tRP), the state of MR is ignored if PFO is exter- nally forced low, to facilitate enabling the battery fresh- ness seal. MR has an internal 70µA pull-up current, so it can be left open if it is not used. This input can be driven with TTL- or CMOS-logic levels, or with open-drain/collec- tor outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function; exter- nal debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environ- ment, connect a 0.1µF capacitor from MR to ground to provide additional noise immunity. Reset Outputs A microprocessor’s (µP’s) reset input starts the µP in a known state. These MAX793/MAX794/MAX795 µP supervisory circuits assert a reset to prevent code exe- cution errors during power-up, power-down, and VLOWLINE (MAX793/MAX794) VRESET (PULLED UP TO VCC) VRESET (MAX793/MAX794) (PFO FOLLOWS PFI) VCE OUT VBATT VWDO (MAX793/MAX794) VBOK (MAX793) MAX794: VRESET IN = VCC (VRST IN / VRST) PFO (MAX793/MAX794) BATT ON SHOWN FOR VCC = 0V to 3.3V, VBATT = 3.6V, CE IN = GND. TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE. 5 µs VSW VCC VRST VLL tRP 25 µs 25 µs 25 µs 25 µs tRP tRP/2 tRP/2 Figure 1. Timing Diagram, VCC Rising |
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