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PGA900 Datasheet(PDF) 11 Page - Texas Instruments |
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PGA900 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 138 page  615 ± G% ENOB 6.02 (1) PGA900 www.ti.com SLDS209A – JANUARY 2015 – REVISED MAY 2015 P Gain (Chopper Stabilized) (continued) over operating free-air temperature range at VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency response(1) Gain = 400 V/V, <1 kHz ±0.1 %V/V Depends on selected gain, Common mode voltage range V bridge supply and sensor span (2) Common mode rejection ratio FCM= 50 Hz at Gain = 5 V/V 110 dB Input impedance 10 M Ω (2) Common Mode at P Gain Input and Output has two constraints: (a) The single-ended voltage of positive/negative pin at the P Gain input should be between 0.3 and 1.8 V. (b) The single-ended voltage of positive/negative pin at the P Gain output should be between 0.1 and 2 V. 6.14 P Analog-to-Digital Converter over operating free-air temperature range at VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Sigma delta modulator frequency 1 MHz ADC voltage input range –2.5 2.5 V Number of bits 24 bits VINPP=VINPN, including gain noise, ADC reference noise, ADC thermal noise, and ADC quantization noise, sampling rate = ENOB(1) 128 µs, across temperature PGAIN= 5 V/V 15 bits PGAIN= 400 V/V 11 bits ADC 2's complement code for –2.5- 2's complement 800000hex V differential input ADC 2's complement code for 0-V 000000hex differential input ADC 2's complement code for 2.5-V 7FFFFFhex differential input Sample period control bit = 0b0 64 Output sample period µs Sample period control bit = 0b1 128 Sample interrupt control bit = 0b0 1 Output sample interrupt samples Sample interrupt control bit = 0b1 4 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: PGA900 |
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