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MAX7490-MAX7491 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX7490-MAX7491 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 18 page Dual Universal Switched-Capacitor Filters 8 _______________________________________________________________________________________ _______________Detailed Description The MAX7490/MAX7491 are universal switched-capaci- tor filters designed with a fixed internal fCLK/fO ratio of 100:1. Operating modes use external resistors connect- ed in different arrangements to realize different filter functions (highpass, lowpass, bandpass, notch) in all of the classical filter topologies (Butterworth, Bessel, ellip- tic, Chebyshev). Figure 1 shows a block diagram. Clock Signal External Clock The MAX7490/MAX7491 switched-capacitor filters are designed for use with external clocks that have a 50% ±5% duty cycle. When using an external clock, drive the EXTCLK pin high or connect to VDD. Drive CLK with CMOS logic levels (GND and VDD). Varying the rate of the external clock adjusts the center frequency of the filter: fO = fCLK /100 Internal Clock When using the internal oscillator, drive the EXTCLK pin low or connect to GND and connect a capacitor (COSC) between CLK and GND. The value of the capacitor (COSC) determines the oscillator frequency as follows: fOSC (kHz) = 135 x 103 / COSC (pF) Since COSC is in the low picofarads, minimize the stray capacitance at CLK so that it does not affect the inter- nal oscillator frequency. Varying the frequency of the internal oscillator adjusts the filter’s center frequency by a 100:1 clock-to-center frequency ratio. For example, an internal oscillator frequency of 135kHz produces a nominal center frequency of 1.35kHz. NAME PIN FILTER A FILTER B FUNCTION LP_ 1 16 2nd-Order Lowpass Filter Output BP_ 2 15 2nd-Order Bandpass Filter Output N_/HP_ 3 14 2nd-Order Notch/Highpass Filter Output INV_ 4 13 Inverting Input of Filter Summing Op Amp S_ 5 12 Summing Input. The connection of the summing input, along with the other resistor connections, determine the circuit topology (mode) of each 2nd- order section. S_ must never be left floating. SHDN 6 Shutdown Input. Drive SHDN low to enable shutdown mode; drive high or connect to VDD for normal operation. GND 7 Ground Pin VDD 8 Positive Supply. VDD should be bypassed with a 0.1 µF capacitor to GND. A low-noise supply is recommended. Input +5V for MAX7490 or +3V for MAX7491. CLK 9 Clock Input. Connect to an external capacitor (COSC) between CLK and ground to set the internal oscillator frequency. For external clock operation, drive with a CMOS-level clock. The duty cycle of the external clock should be between 45% and 55% for best performance. EXTCLK 10 External/Internal Clock Select Input. Connect EXTCLK to VDD when driving CLK externally. Connect to GND when using the internal oscillator. COM 11 Common Pin. Biased internally at VDD/2. Bypass externally to GND with 0.1 µF capacitor. To override the internal biasing, drive with an external low- impedance source. Pin Description |
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