DRV8839

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SLVSBN4A – JANUARY 2013 – REVISED JANUARY 2014

FUNCTIONAL DESCRIPTION

Bridge Control

The DRV8839 is controlled using separate enable and input pins for each ½-H-bridge.

The following table shows the logic for the DRV8839:

ENx

INx

OUTx

0

X

Z

1

0

L

1

1

H

Sleep Mode

If the nSLEEP pin is brought to a logic-low state, the DRV8839 will enter a low-power sleep mode. In this state

all unnecessary internal circuitry is powered down.

Power Supplies and Input Pins

The input pins may be driven within their recommended operating conditions with or without the VCC and VM

power supplies present. No leakage current path will exist to the supply. There is a weak pulldown resistor

(approximately 100 k

Ω) to ground on each input pin.

VCC and VM may be applied and removed in any order. When VCC is removed, the device will enter a low

power state and draw very little current from VM. If the supply voltage is between 1.8 V and 7 V, VCC and VM

may be connected together.

The VM voltage supply does not have any undervoltage lockout protection (UVLO), so as long as VCC > 1.8 V,

the internal device logic will remain active. This means that the VM pin voltage may drop to 0 V, however, the

load may not be sufficiently driven at low VM voltages.

Protection Circuits

The DRV8839 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this

analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled. After

approximately 1 ms, the bridge will be re-enabled automatically.

Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor

winding will all result in an overcurrent shutdown.

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled. Once the die temperature

has fallen to a safe level operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all circuitry in

the device is disabled and internal logic is reset. Operation resumes when VCC rises above the UVLO threshold.

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Product Folder Links: DRV8839