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MAX6825SUK-T Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX6825SUK-T Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 9 page Resets are issued to the µP during power-up, power- down, and brownout conditions. The Typical Operating Characteristics show a graph of the MAX6821– MAX6825’s Maximum VCC Transient Duration vs. Reset Threshold Overdrive, for which reset pulses are not generated. The graph was produced using negative- going VCC pulses, starting at the standard monitored voltage and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negative- going VCC transient can typically have without trigger- ing a reset pulse. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 20µs or less will not trigger a reset pulse. Watchdog Software Considerations One way to help the watchdog timer monitor software execution more closely is to set and reset the watch- dog input at different points in the program, rather than pulsing the watchdog input high-low-high or low-high- low. This technique avoids a stuck loop, in which the watchdog timer would continue to be reset inside the loop, keeping the watchdog from timing out. Figure 5 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should hang in any subroutine, the problem would quickly be corrected, since the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. As described in the Watchdog Input Current section, this scheme results in higher time average WDI input current than does leaving WDI low for the majority of the timeout period and periodically pulsing it low-high-low. Low-Voltage SOT23 µP Supervisors with Manual Reset and Watchdog Timer _______________________________________________________________________________________ 7 Figure 3. Watchdog Timing Relationship Figure 4. Interfacing Open-Drain RESET to µPs with Bidirectional Reset I/O VCC tWD tRP tRP tRST WDI RESET* *RESET IS THE INVERSE OF RESET. MAX6822 RESET GENERATOR GND GND VCC VCC RESET RESET µP Figure 5. Watchdog Flow Diagram START SET WDI HIGH PROGRAM CODE SUBROUTINE OR PROGRAM LOOP SET WDI LOW RETURN MAX6823 µP VCC VCC VCC GND MANUAL RESET RESET I/O RESET MR WDI Typical Operating Circuit |
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