Microprocessor Supervisory Circuits

4

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µA

0.10

±5

OSC IN Leakage Current

µs

12

RESET-to-CE OUT Delay

2.7

CE OUT Output Voltage High

(Reset Active)

3.5

ns

6

10

CE IN-to-CE OUT Propagation

Delay (Note 8)

mA

0.1

0.75

2.0

CE OUT Short-Circuit Current

(Reset Active)

Ω

75

150

CE IN-to-CE OUT Resistance

(Note 7)

µA

±0.005

±1

CE IN Leakage Current

60

PFI-to-PFO Delay

µs

25

µA

1

15

100

PFO Output Short-Circuit

Current

CONDITIONS

3.5

PFO Output Voltage

V

0.4

nA

±0.01

±25

PFI Leakage Current

1.225

1.25

1.275

PFI Input Threshold

V

1.2

1.25

1.3

UNITS

MIN

TYP

MAX

PARAMETER

OSC SEL = 0V

Power-down

50

Disable mode,

–

CE OUT = 0V

Enable mode

Disable mode

Output source current

Note 3: “+” = battery-discharging current, “--” = battery-charging current.

Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and

do not vary with process or temperature.

Note 5: RESET is an open-drain output and sinks current only.

disabling the watchdog function.

Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.

ELECTRICAL CHARACTERISTICS (continued)

unless otherwise noted.)

kHz

50

OSC IN Frequency Range

µA

10

100

OSC SEL Input Pull-Up Current

µA

10

100

OSC IN Input Pull-Up Current

OSC SEL = 0V

OSC SEL = 0V

V

3.65

2.00

OSC IN External Oscillator

Threshold Voltage

kHz

100

OSC IN Frequency with

External Capacitor

OSC SEL = 0V, COSC = 47pF

V

POWER-FAIL COMPARATOR

CHIP-ENABLE GATING

INTERNAL OSCILLATOR