Detailed Description

Many dual-supply processors or multivoltage boards

require one power supply to rise to the proper operat-

ing voltage before another supply is applied. Improper

sequencing can lead to chip latchup, incorrect device

initiation, or long-term reliability degradation. If the vari-

ous supply voltages are not locally generated (coming

from a main system bus, an externally purchased silver

box, or a nonsequenced power management chip),

power-on and power-off sequencing can be difficult to

control or predict. Supply loading can affect turn-

on/turn-off times from board to board.

The MAX6819/MAX6820 provide proper local voltage

sequencing in multisupply systems. The sequencers

use an external N-channel MOSFET to switch the sec-

ondary supply to the load only when the primary supply

is above a desired operating voltage threshold. The N-

channel MOSFET operates in a default off mode when

the primary supply is below the desired threshold or if

neither supply exceeds the sequencer’s UVLO level.

When the primary supply voltage is above the set

threshold, the external MOSFET is driven on. An inter-

nal charge pump fully enhances the external MOSFET

(typ). The charge pump fully enhances the MOSFET to

reduced switch voltage drop. The MOSFET is never dri-

ven on unless the sequencer can provide a minimum

never operates in its higher impedance linear range.

Either supply may act as the primary source, regard-

greater than 2.125V (Figure 1 and Figure 2).

SOT23 Power-Supply Sequencers

_______________________________________________________________________________________

5

PIN

MAX6819

MAX6820

NAME

FUNCTION

11

external MOSFET drive.

2

2

GND

Ground

3

3

SETV

Sequence Threshold Set. Connect to an external resistor-divider network to set the

4

—

EN

—

4

SETD

GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust

5

5

GATE

fully enhance the external N-channel MOSFET.

66

external MOSFET drive.

Pin Description

SETV

( ) FOR MAX6820 ONLY

0.62V

GND

SEQUENCE

DELAY/

LOGIC

GATE

EN (SETD)

GATE DRIVE

CHARGE PUMP

UVLO

Figure 1. Functional Diagram