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ADS58J63 Datasheet(PDF) 1 Page - Texas Instruments |
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ADS58J63 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 87 page  CLKINP/M DAP/M INAP/M PLL x10/x20 DCP/M DDP/M 14bit ADC INBP/M INCP/M 14bit ADC INDP/M DBP/M JESD204B SYNCbCD SYSREFP/M Configuration Registers Digital Block Interleaving Correction 14bit ADC 14bit ADC Digital Block Interleaving Correction Digital Block Interleaving Correction Digital Block Interleaving Correction SYNCbAB TRIGAB TRIGCD TRDYCD JESD204B TRDYAB Burst Mode Burst Mode 4x K*FS/16 FS/8 2x FS/4 2x 4x K*FS/16 FS/8 2x FS/4 2x Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS58J63 SBAS717A – JUNE 2015 – REVISED JUNE 2015 ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device 1 Features 3 Description The ADS58J63 is a low-power, wide-bandwidth, 14- 1 • Quad Channel bit, 500-MSPS, quad-channel, telecom receiver • 14-Bit Resolution device. The ADS58J63 supports a JESD204B serial • Maximum Clock Rate: 500 MSPS interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides • Input Bandwidth (3 dB): 900 MHz uniform input impedance across a wide frequency • On-Chip Dither range and minimizes sample-and-hold glitch energy. • Analog Input Buffer with High-Impedance Input The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency • Output Options: range with very low power consumption. The digital – Rx: Decimate-by-2 and -4 Options with Low- signal processing block includes complex mixers Pass Filter followed by low-pass filters with decimate-by-2 and -4 – 200-MHz Complex Bandwidth or 100-MHz options supporting up to 200-MHz receive bandwidth. Real Bandwidth Support The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a – DPD FB: Burst Mode with 14-Bit Output DPD observation receiver. • 1.9-VPP Differential Full-Scale Input The JESD204B interface reduces the number of • JESD204B Interface: interface lines, thus allowing high system integration – Subclass 1 Support density. An internal phase locked loop (PLL) – 1 Lane per ADC Up to 10 Gbps multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is – Dedicated SYNC pin for pair of channels used to serialize the 14-bit data from each channel. • Support for Multi-Chip Synchronization • 72-Pin VQFN Package (10 mm × 10 mm) Device Information(1) • Key Specifications: PART NUMBER PACKAGE BODY SIZE (NOM) – Power Dissipation: 675 mW/ch ADS58J63 VQFN (72) 10.00 mm x 10.00 mm – Spectral Performance (Un-decimated) (1) For all available packages, see the orderable addendum at the end of the data sheet. – fIN = 190 MHz IF at –1 dBFS: – SNR: 70.4 dBFS Simplified Block Diagram – NSD: –154.4 dBFS/Hz – SFDR: 86 dBc (HD2, HD3), 95 dBFS (non HD2, HD3) – fIN = 370 MHz IF at –3 dBFS: – SNR: 68.5 dBFS – NSD: –152.5 dBFS/Hz – SFDR: 81 dBc (HD2, HD3), 86 dBFS (non HD2, HD3) 2 Applications • Multi-Carrier GSM Cellular Infrastructure Base Stations • Multi-Carrier Multi-Mode Cellular Infrastructure Base Stations • Telecommunications Receiver • Telecom DPD Observation Receiver 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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