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IRS25091SPbF

Switching and Timing Relationships

The relationships between the input and output signals of the IRS25091 are illustrated below in Figures 3, 4. From these figures, we

Figure 3: Switching time waveforms

Figure 4: Input/output timing diagram

Deadtime

This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC

portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum

deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned

off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserter whenever the

external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the

deadtime period and the relationship between the output gate signals.

The deadtime circuitry of the IRS25091 is matched with respect to the high- and low-side outputs. Figure 6 defines the two deadtime

Matched Propagation Delays

The IRS25091 is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at