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TSE2004GB2B0 Datasheet(PDF) 11 Page - Integrated Device Technology |
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TSE2004GB2B0 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 31 page 11 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Device Diagram Device Interface The TSE2004GB2B0 behaves as a slave device in the I2C Bus protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and R/W# bit (as described in the I2C Bus Operating Mode table), terminated by an acknowledge bit. The TSE2004GB2B0 does not initiate clock stretching which is an optional I2C Bus feature. In accordance with the I2C Bus definition, the device uses three (3) built-in, 4-bit Device Type Identifier Codes (DTIC) and the state of SA0, SA1, and SA2 to generate an I2C Bus Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the SWPn, RSPn, or CSWP operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). Serial Address Selection Inputs SA0, SA1, and SA2 inputs are directly combined with the DTIC and the EE page address bit to qualify SMBus addresses. Each of the SA pins is tied to VDDSPD or VSSSPD and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins. I2C Bus Addressing Modes Logical Serial Address(LSA) SA2 SA1 SA0 000 0 0 0 001 0 0 1 010 0 1 0 011 0 1 1 100 1 0 0 101 1 0 1 110 1 1 0 111 1 1 1 Note 1: 0 = VSSSPD, 1 = VDDSPD |
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