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TSE2002GB2A1 Datasheet(PDF) 6 Page - Integrated Device Technology |
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TSE2002GB2A1 Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 30 page 6 of 30 July 17, 2012 AC Characteristics 1. For a RESTART condition, or following a write cycle. 2. Guaranteed by design and characterization, not necessarily tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or rising edge of SDA. 4. The TSE2002GB2A1 does not initiate clock stretching which is an optional I2C bus feature 5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of tTIMEOUT,MIN. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller and embedded controller and most devices that can master the SMBus. Some devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds SCL low for tTIMEOUT,MAX or longer. 6. The temperature sensor family of devices are not required to support the SMBus ALERT function. Parameter Symbol VDDSPD > 2.2 V Units Min. Max. Clock Frequency fSCL 10 400 kHz Clock Pulse Width High Time tHIGH 600 ns Clock Pulse Width Low Time tLOW 5 1300 ns Detect clock low timeout, Capabilities Register bit 6 =1 tTIMEOUT 6 25 35 ms SDA Rise Time tR 2 300 ns SDA Fall Time tF 2 20 300 ns Data In Setup Time tSU:DAT 100 ns Data In Hold Time tHD:DI 0ns Data Out Hold Time tHD:DAT 200 900 ns Start Condition Setup Time tSU:STA 1 600 ns Start Condition Hold Time tHD:STA 600 ns Stop Condition Setup Time tSU:STO 600 ns Time Between Stop Condition and Next Start Condition tBUF 1300 ns Write Time tW 4.5 ms |
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