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89HPES32NT8BG2 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 89HPES32NT8BG2
Description  Low latency cut-through architecture
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

89HPES32NT8BG2 Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT 89HPES32NT8BG2 Datasheet
8 of 35
December 17, 2013
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER1
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: FAILOVER3
2nd Alternate function pin type: Input
2nd Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER2
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: P8LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Up Status output.
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: IOEXPINTN
1st Alternate function pin type: Input
1st Alternate function: IO expander interrupt.
2nd Alternate function pin name: P8ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Active Status Output.
Signal
Type
Name/Description
STK0CFG0
I
Stack 0 Configuration. This pin selects the configuration of stack 0.
STK1CFG0
I
Stack 1 Configuration. This pin selects the configuration of stack 1.
STK2CFG0
I
Stack 2 Configuration. This pin selects the configuration of stack 2.
STK3CFG0
I
Stack 3 Configuration. This pin selects the configuration of stack 3.
Table 6 Stack Configuration Pins
Signal
Type
Name/Description
CLKMODE[1:0]
I
Clock Mode. These signals determine the port clocking mode used by ports of the
device.
GCLKFSEL
I
Global Clock Frequency Select. These signals select the frequency of the GCLKP
and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
Table 7 System Pins (Part 1 of 2)
Signal
Type
Name/Description
Table 5 General Purpose I/O Pins (Part 2 of 2)


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