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89HPES12NT12G2 Datasheet(PDF) 2 Page - Integrated Device Technology |
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89HPES12NT12G2 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 32 page  IDT 89HPES12NT12G2 Datasheet 2 of 32 December 16, 2013 • Common clock • Non-common clock • Local port clock with SSC (spread spectrum setting) and port reference clock input Hot-Plug and Hot Swap – Hot-plug controller on all ports • Hot-plug supported on all downstream switch ports – All ports support hot-plug using low-cost external I2C I/O expanders – Configurable presence-detect supports card and cable appli- cations – GPE output pin for hot-plug event notification • Enables SCI/SMI generation for legacy operating system support – Hot-swap capable I/O Power Management – Supports D0, D3hot and D3 power management states – Active State Power Management (ASPM) • Supports L0, L0s, L1, L2/L3 Ready, and L3 link states • Configurable L0s and L1 entry timers allow performance/ power-savings tuning – SerDes power savings • Supports low swing / half-swing SerDes operation • SerDes associated with unused ports are turned off • SerDes associated with unused lanes are placed in a low power state Reliability, Availability, and Serviceability (RAS) – ECRC support – AER on all ports – SECDED ECC protection on all internal RAMs – End-to-end data path parity protection – Checksum Serial EEPROM content protected – Ability to generate an interrupt (INTx or MSI) on link up/down transitions Initialization / Configuration – Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization – Common switch configurations are supported with pin strap- ping (no external components) – Supports in-system Serial EEPROM initialization/program- ming On-Die Temperature Sensor – Range of 0 to 127.5 degrees Celsius – Three programmable temperature thresholds with over and under temperature threshold alarms – Automatic recording of maximum high or minimum low temperature 9 General Purpose I/O Test and Debug – Ability to inject AER errors simplifies in system error handling software validation – On-chip link activity and status outputs available for several ports – Per port link activity and status outputs available using external I2C I/O expander for all remaining ports – Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Standards and Compatibility – PCI Express Base Specification 2.1 compliant – Implements the following optional PCI Express features • Advanced Error Reporting (AER) on all ports • End-to-End CRC (ECRC) • Access Control Services (ACS) • Device Serial Number Enhanced Capability • Sub-System ID and Sub-System Vendor ID Capability • Internal Error Reporting • Multicast • VGA and ISA enable • L0s and L1 ASPM • ARI Power Supplies – Requires three power supply voltages (1.0V, 2.5V, and 3.3V) Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with 1mm ball spacing Product Description With Non-Transparent Bridging functionality and innovative Switch Partitioning feature, the PES12NT12G2 allows true multi-host or multi- processor communications in a single device. Integrated DMA control- lers enable high-performance system design by off-loading data transfer operations across memories from the processors. Each lane is capable of 5 GT/s link speed in both directions and is fully compliant with PCI Express Base Specification 2.1. A non-transparent bridge (NTB) is required when two PCI Express domains need to communicate to each other. The main function of the NTB block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains. The major function- alities of the NTB block are summarized in Table 1. |
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