CMOS IC Application Note

S-8209B Series Usage Guidelines

Seiko Instruments Inc.

5

1. 2. 2 Status to inhibit charge

Following is about the status to inhibit charge, for example, the S-8209B (1) detects overcharge, the S-8209B (2)

and (3) are in the normal status.

high impedance.

The CTLC2 pin gets the level of VSS2 pin by the high impedance CO1 pin. Thus the S-8209B (2) goes in the

in high impedance.

the level of VSS3 pin by the high impedance CO2 pin. The S-8209B (3) also goes in the overcharge status after

The status of each pin in this case is shown in Table 2.

Table 2

CTLC pin

CTLD pin

Status of battery

CO pin

DO pin

CTLC1 = VDD1

CTLD1 = VDD1

≤ BAT1

CO1 = High-Z

DO1 = VDD1

CTLC2 = VSS2

CTLD2 = VDD1

CO2 = High-Z

DO2 = VDD2

CTLC3 = VSS3

CTLD3 = VDD2

CO3 = High-Z

DO3 = VDD3

CO3 pin. In this case, charging via a charger connected between P

+ and P− is inhibited.

By this operation the overcharge status is transmitted from the top (S-8209B (1)) to the bottom (S-8209B (3)),

from the CO pin to the CTLC pin.