3 of 31

March 27, 2008

IDT 89HPES8T5 Data Sheet

Figure 3 Configuration Option

SMBus Interface

The PES8T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES8T5, allowing every

configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of

the PES8T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an

external Hot-Plug I/O expander.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In

the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these

address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up

on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in

Table 1.

As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure

4(a), the master and slave SMBuses are tied together and the PES8T5 acts both as a SMBus master as well as a SMBus slave on this bus. This

requires that the SMBus master or processor that has access to PES8T5 registers supports SMBus arbitration. In some systems, this SMBus master

interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support

these systems, the PES8T5 may be configured to operate in a split configuration as shown in Figure 4(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.

The PES8T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the

serial EEPROM.

Bit

Slave

SMBus

Address

Master

SMBus

Address

1

SSMBADDR[1]

MSMBADDR[1]

2

SSMBADDR[2]

MSMBADDR[2]

3

SSMBADDR[3]

MSMBADDR[3]

4

0

MSMBADDR[4]

5

SSMBADDR[5]

1

61

0

71

1

Table 1 Master and Slave SMBus Address Assignment

x1

x1

x1

x1

x4

PES8T5

x1

x1

x1

x1

x4

PES8T5