2:1 1.5V PCIE GEN1-2-3 CLOCK MUX

2

REVISION A 09/30/14

9DMU0131 DATASHEET

Pin Configuration

Power Management Table

Power Connections

Pin Descriptions

16 15 14 13

GNDR 1

12 VDD1.5

VDDR1.5 2

11 GND

VDDR1.5 3

10 DIF0#

GNDR 4

9 DIF0

5678

16-pin VFQFPN, 3x3 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

Note: Paddle may be connected to ground for thermal

purposes. It is not required electrically.

9DMU0131

v prefix indicates internal 120KOhm pull down resistor

True O/P

Comp. O/P

0

Running

Running

Running

1

Running

Low

Low

DIF_IN

OEx# Pin

DIFx

VDD

GND

21

34

12

11

Note: Pins 2 and 3 should be decoupled separately to

pins 1 and 4 respectively.

DIF outputs

Description

Pin Number

Input A receiver analog

Input B receiver analog

Pin#

Pin Name

Type

Pin Description

1

GNDR

GND

Analog Ground pin for the differential input (receiver)

2

VDDR1.5

PWR

1.5V power for differential input clock (receiver). This VDD should be treated as an Analog

power rail and filtered appropriately.

3

VDDR1.5

PWR

1.5V power for differential input clock (receiver). This VDD should be treated as an Analog

power rail and filtered appropriately.

4

GNDR

GND

Analog Ground pin for the differential input (receiver)

5

DIF_INB

IN

HCSL Differential True input

6

DIF_INB#

IN

HCSL Differential Complement Input

7vSW_MODE

IN

Switch Mode. This pin selects either asynchronous or glitch-free switching of the mux. Use

asynchronous mode if 0 or 1 of the input clocks is running. Use glitch-free mode if both input

clocks are running. This pin has an internal pull down resistor of ~120kohms.

0 = asynchronous mode

1 = glitch-free mode

8^OE0#

IN

Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.

1 =disable outputs, 0 = enable outputs

9

DIF0

OUT

Differential true clock output

10

DIF0#

OUT

Differential Complementary clock output

11

GND

GND

Ground pin.

12

VDD1.5

PWR

Power supply, nominally 1.5V

13

NC

N/A

No Connection.

14

^SEL_A_B#

IN

Input to select differential input clock A or differential input clock B. This input has an internal

pull-up resistor.

0 = Input B selected, 1 = Input A selected.

15

DIF_INA

IN

HCSL Differential True input

16

DIF_INA#

IN

HCSL Differential Complement Input