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MAX5821 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # MAX5821
Description  Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5821 Datasheet(HTML) 3 Page - Maxim Integrated Products

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Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k
Ω, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Hysteresis
0.05
VDD
V
Input Leakage Current
Digital inputs = 0 or VDD
±0.1
±1µA
Input Capacitance
6pF
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage
VOL
ISINK = 3mA
0.4
V
Three-State Leakage Current
IL
Digital inputs = 0 or VDD
±0.1
±1µA
Three-State Output Capacitance
6pF
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.5
V/µs
Voltage-Output Settling Time
To 1/2LSB code 100 hex to 300 hex or
300 hex to 100 hex (Note 5)
412
µs
Digital Feedthrough
Code = 000 hex, digital inputs from 0 to VDD
0.2
nV-s
Digital-to-Analog Glitch Impulse
Major carry transition (code = 1FF hex to 200
hex and 200 hex to 1FF hex)
12
nV-s
DAC-to-DAC Crosstalk
2.4
nV-s
POWER SUPPLIES
Supply Voltage Range
VDD
2.7
5.5
V
All digital inputs at 0 or VDD = 3.6V
115
205
Supply Current with No Load
IDD
All digital inputs at 0 or VDD = 5.5V
135
215
µA
Power-Down Supply Current
IDDPD
All digital inputs at 0 or VDD = 5.5V
0.3
1
µA
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
START Condition Hold Time
tHD,STA
0.6
µs
SCL Pulse Width Low
tLOW
1.3
µs
SCL Pulse Width High
tHIGH
0.6
µs
Repeated START Setup Time
tSU,STA
0.6
µs
Data Hold Time
tHD,DAT
0
0.9
µs
Data Setup Time
tSU,DAT
100
ns
SDA and SCL Receiving
Rise Time
tr
(Note 5)
0
300
ns
SDA and SCL Receiving
Fall Time
tf
(Note 5)
0
300
ns
SDA Transmitting Fall Time
tf
(Note 5)
20 +
0.1Cb
250
ns


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